MC9S12XD256CAL Datasheet, PDF (422/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
CAN node 1
MCU
CAN Controller
(MSCAN)
CAN node 2
TXCAN
RXCAN
Transceiver
CAN_H
CAN_L
CAN Bus
CAN node n
Figure 10-2. CAN System
10.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the MSCAN.
10.3.1 Module Memory Map
Figure 10-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The
register address results from the addition of base address and address offset. The base address is
determined at the MCU level and can be found in the MCU memory map description. The address offset
is defined at the module level.
The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is
determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the
first address of the module address offset.
The detailed register descriptions follow in the order they appear in the register map.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
CANCTL0
R
RXFRM
W
RXACT
CSWAI
SYNCH
TIME
WUPE SLPRQ INITRQ
0x0001
CANCTL1
R
CANE
W
CLKSRC LOOPB LISTEN
BORM
WUPM
SLPAK
INITAK
= Unimplemented or Reserved
u = Unaffected
Figure 10-3. MSCAN Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
422
Freescale Semiconductor