MC9S12XD256CAL Datasheet, PDF (437/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
NOTE
The CANTBSEL register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK=1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
Read: Find the lowest ordered bit set to 1, all other bits will be read as 0
Write: Anytime when not in initialization mode
Table 10-15. CANTBSEL Register Field Descriptions
Field
2:0
TX[2:0]
Description
Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG
register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit
buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx
bit is cleared and the buffer is scheduled for transmission (see Section 10.3.2.7, “MSCAN Transmitter Flag
Register (CANTFLG)”).
0 The associated message buffer is deselected
1 The associated message buffer is selected, if lowest numbered bit
The following gives a short programming example of the usage of the CANTBSEL register:
To get the next available transmit buffer, application software must read the CANTFLG register and write
this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The
value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the
Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1.
Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered
bit position set to 1 is presented. This mechanism eases the application software the selection of the next
available Tx buffer.
• LDD CANTFLG; value read is 0b0000_0110
• STD CANTBSEL; value written is 0b0000_0110
• LDD CANTBSEL; value read is 0b0000_0010
If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.
10.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC)
The CANIDAC register is used for identifier acceptance control as described below.
R
W
Reset:
7
6
5
4
3
2
1
0
0
0
IDHIT2
IDHIT1
IDAM1
IDAM0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-15. MSCAN Identifier Acceptance Control Register (CANIDAC)
0
IDHIT0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
437