MC9S12XD256CAL Datasheet, PDF (645/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 17 Memory Mapping Control (S12XMMCV2)
Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses is the following:
• An aligned word access to a PRR will take 2 bus cycles.
• A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
• A byte access to a PRR will take 2 cycles.
Table 17-22. PRR Listing
PRR Name
PORTA
PORTB
DDRA
DDRB
PORTC
PORTD
DDRC
DDRD
PORTE
DDRE
MMCCTL0
MODE
PUCR
RDRIV
EBICTL0
EBICTL1
Reserved
MMCCTL1
ECLKCTL
Reserved
PORTK
DDRK
PRR Local Address
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0012
$0013
$001C
$001D
$0032
$0033
PRR Location
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
MMC
MMC
PIM
PIM
EBI
EBI
MMC
MMC
PIM
PIM
PIM
PIM
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
645