MC9S12XD256CAL Datasheet, PDF (1014/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Table 24-40. PIFP Field Descriptions
Field
Description
7–0
PIFP[7:0]
Interrupt Flags Port P
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a logic level “1” clears the associated flag.
24.0.5.42 Port H Data Register (PTH)
7
R
PTH7
W
6
PTH6
5
PTH5
4
PTH4
3
PTH3
2
PTH2
1
PTH1
0
PTH0
Routed
SPI
SS1
SCK1
MOSI1
MISO1
Reset
0
0
0
0
0
0
0
0
Figure 24-44. Port H Data Register (PTH)
Read: Anytime.
Write: Anytime.
Port H pins 7–0 are associated with the routed SPI1.
These pins can be used as general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
The routed SPI1 function takes precedence over the general purpose I/O function if the routed SPI1 is
enabled. Refer to SPI section for details.
24.0.5.43 Port H Input Register (PTIH)
7
R PTIH7
6
PTIH6
5
PTIH5
4
PTIH4
3
PTIH3
2
PTIH2
1
PTIH1
0
PTIH0
W
Reset¹
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 24-45. Port H Input Register (PTIH)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
1016
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor