MC9S12XD256CAL Datasheet, PDF (1214/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
START
Read: FCLKDIV register
Clock Register
Written
Check
FDIVLD
no
Set?
NOTE: FCLKDIV needs to
be set once after each reset.
yes
Write: FCLKDIV register
Read: FSTAT register
Address, Data,
Command
Buffer Empty Check
CBEIF
no
Set?
yes
Access Error and
Protection Violation
Check
ACCERR/
PVIOL
Set?
no
yes
Write: FSTAT register
Clear ACCERR/PVIOL 0x30
Write: Flash Address to start
1. _{compression and number of word}
addresses to compress
2.
Write: FCMD register
Data Compress Command 0x06
3.
Write: FSTAT register
Clear CBEIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
CCIF
Set?
no
yes
Read: FDATA registers
Data Compress Signature
Signature
no
Valid?
yes
EXIT
Erase and Reprogram
Flash Sector(s) Compressed
Figure 29-24. Example Data Compress Command Flow
1216
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor