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MC9S12XD256CAL Datasheet, PDF (446/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG). | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
1 Not applicable for receive buffers
2 Read-only for CPU
3 Read-only for CPU
Figure 10-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identiï¬ers. The mapping of standard identiï¬ers into the IDR registers is shown in Figure 10-25.
All bits of the receive and transmit buffers are âxâ out of reset because of RAM-based implementation1.
All reserved or unused bits of the receive and transmit buffers always read âxâ.
1. Exception: The transmit priority registers are 0 out of reset.
MC9S12XDP512 Data Sheet, Rev. 2.21
446
Freescale Semiconductor
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