MC9S12XD256CAL Datasheet, PDF (674/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.4.2.1.1 Expansion of the Local Address Map
Expansion of the CPU Local Address Map
The program page index register in MMC allows accessing up to 4 Mbyte of FLASH or ROM in the global
memory map by using the eight page index bits to page 256 16 Kbyte blocks into the program page
window located from address 0x8000 to address 0xBFFF in the local CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions
(see Section 18.5.1, “CALL and RTC Instructions).
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64-kilobyte local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper
16-kilobyte block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that
all reset and interrupt vectors point to locations in this area or to the other unpaged sections of the local
CPU memory map.
Table 18-19 Table 18-12 summarizes mapping of the address bus in Flash/External space based on the
address, the PPAGE register value and value of the ROMHM bit in the MMCCTL1 register.
Table 18-19. Global FLASH/ROM Allocated
Local
CPU Address
ROMHM
External
Access
Global Address
0x4000–0x7FFF
0
No
0x7F_4000 –0x7F_7FFF
1
0x8000–0xBFFF
N/A
N/A
Yes
No¹
Yes¹
0x14_4000–0x14_7FFF
0x40_0000–0x7F_FFFF
0xC000–0xFFFF
N/A
No
0x7F_C000–0x7F_FFFF
1 _{The internal or the external bus is accessed based on the size of the memory resources}
implemented on-chip. Please refer to Figure 1-23 for further details.
The RAM page index register allows accessing up to 1 Mbyte –2 Kbytes of RAM in the global memory
map by using the eight RPAGE index bits to page 4 Kbyte blocks into the RAM page window located in
the local CPU memory space from address 0x1000 to address 0x1FFF. The EEPROM page index register
EPAGE allows accessing up to 256 Kbytes of EEPROM in the system by using the eight EPAGE index
bits to page 1 Kbyte blocks into the EEPROM page window located in the local CPU memory space from
address 0x0800 to address 0x0BFF.
MC9S12XDP512 Data Sheet, Rev. 2.21
674
Freescale Semiconductor