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MC9S12XD256CAL Datasheet, PDF (1276/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG). | |||
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Appendix A Electrical Characteristics
In Figure A-10 the timing diagram for slave mode with transmission format CPHA = 1 is depicted.
SS
(Input)
SCK
(CPOL = 0)
(Input)
SCK
(CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
1
2
12
4
4
12
See
Note
9
Slave MSB OUT
7
5
6
MSB IN
11
Bit 6 . . . 1
Bit 6 . . . 1
3
13
13
8
Slave LSB OUT
LSB IN
NOTE: Not deï¬ned
Figure A-10. SPI Slave Timing (CPHA = 1)
In Table A-27 the timing characteristics for slave mode are listed.
Table A-27. SPI Slave Mode Timing Characteristics
Num C
Characteristic
Symbol
Min
1
D SCK frequency
fsck
DC
1
D SCK period
tsck
4
2
D Enable lead time
tlead
4
3
D Enable lag time
tlag
4
4
D Clock (SCK) high or low time
twsck
4
5
D Data setup time (inputs)
tsu
8
6
D Data hold time (inputs)
thi
8
7
D Slave access time (time to data active)
ta
â
8
D Slave MISO disable time
tdis
â
9
D Data valid after SCK edge
tvsck
â
10
D Data valid after SS fall
tvss
â
11
D Data hold time (outputs)
tho
20
12
D Rise and fall time inputs
trï¬
â
13
D Rise and fall time outputs
trfo
â
1 0.5 tbus added due to internal synchronization delay
Typ
Max
Unit
â
1/4
fbus
â
â
tbus
â
â
tbus
â
â
tbus
â
â
tbus
â
â
ns
â
â
ns
â
20
ns
â
22
ns
â
29 + 0.5 â
tbus1
ns
â
29 + 0.5 â
tbus1
ns
â
â
ns
â
8
ns
â
8
ns
1278
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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