MC9S12XD256CAL Datasheet, PDF (391/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG).

Clock Source 7
High
PWMCNT6
Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
Low
PWCNT7
Clock Source 5
Period/Duty Compare
High
PWMCNT4
Low
PWCNT5
PWM7
Clock Source 3
Period/Duty Compare
High
PWMCNT2
Low
PWCNT3
PWM5
Clock Source 1
Period/Duty Compare
High
PWMCNT0
Low
PWCNT1
PWM3
Period/Duty Compare
PWM1
Figure 8-24. PWM 16-Bit Mode
Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order
bytes PWMEx bits have no effect and their corresponding PWM output is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
391