|
MC9S12XD256CAL Datasheet, PDF (547/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG). | |||
|
◁ |
13.3.0.4 PIT Multiplex Register (PITMUX)
Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
PMUX3
0
2
PMUX2
0
Figure 13-6. PIT Multiplex Register (PITMUX)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 13-4. PITMUX Field Descriptions
1
PMUX1
0
0
PMUX0
0
Field
Description
3:0
PMUX[3:0]
PIT Multiplex Bits for Timer Channel 3:0 â These bits select if the corresponding 16-bit timer is connected to
micro time base 1 or 0. If PMUX is modiï¬ed, the corresponding 16-bit timer is immediately switched to the other
micro time base.
0 The corresponding 16-bit timer counts with micro time base 0.
1 The corresponding 16-bit timer counts with micro time base 1.
13.3.0.5 PIT Interrupt Enable Register (PITINTE)
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
PINTE3
0
2
PINTE2
0
Figure 13-7. PIT Interrupt Enable Register (PITINTE)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 13-5. PITINTE Field Descriptions
1
PINTE1
0
0
PINTE0
0
Field
Description
3:0
PINTE[3:0]
PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 â These bits enable an interrupt service request
whenever the time-out ï¬ag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)
enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF ï¬ag has to be
cleared ï¬rst.
0 Interrupt of the corresponding PIT channel is disabled.
1 Interrupt of the corresponding PIT channel is enabled.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
547
|
▷ |