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MC9S12XD256CAL Datasheet, PDF (1129/1348 Pages) Freescale Semiconductor, Inc – This specification describes the function of the clocks and reset generator (CRG). | |||
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
27.4.2.1 Erase Verify Command
The erase verify operation will verify that a Flash block is erased.
An example ï¬ow to execute the erase verify operation is shown in Figure 27-25. The erase verify command
write sequence is as follows:
1. Write to a Flash block address to start the command write sequence for the erase verify command.
The address and data written will be ignored. Multiple Flash blocks can be simultaneously erase
veriï¬ed by writing to the same relative address in each Flash block.
2. Write the erase verify command, 0x05, to the FCMD register.
3. Clear the CBEIF ï¬ag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify
command.
After launching the erase verify command, the CCIF ï¬ag in the FSTAT register will set after the operation
has completed unless a new command write sequence has been buffered. The number of bus cycles
required to execute the erase verify operation is equal to the number of addresses in a Flash block plus 14
bus cycles as measured from the time the CBEIF ï¬ag is cleared until the CCIF ï¬ag is set. Upon completion
of the erase verify operation, the BLANK ï¬ag in the FSTAT register will be set if all addresses in the
selected Flash blocks are veriï¬ed to be erased. If any address in a selected Flash block is not erased, the
erase verify operation will terminate and the BLANK ï¬ag in the FSTAT register will remain clear. The
MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the erase verify
operation.
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
1131
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