TCC720 Datasheet, PDF (88/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
UART / IrDA
Preliminary Spec 0.51
UART/IrDA Control Register (CR)
31 30 29 28 27 26 25 24 23 22 21 20
0
15 14 13 12 11 10 9 8 7 6 5 4
0
NO BK TF RF FIFO
0x8000060C
19 18 17 16
32
PR
10
ST B7
NO [9]
0
1
Start Bit Width Check
Check if the pulse width of start bit is more than 0.5 bit duration of baud rate
Don’t check the pulse width of start bit (used only for test or boot mode)
BK [8]
0
1
Break Control Bit
Normal operation
Bit ‘0’ is transmitted regardless of THR
TF [7]
1
Reset Transmitter FIFO
The transmitter FIFO is cleared
RF [6]
1
Reset Receiver FIFO
The receiver FIFO is cleared
FIFO [5:4]
RX FIFO Level Select
n
0 = 1byte FIFO, 1 = 2 byte FIFO
2 = 4 byte FIFO, 3 = 7 byte FIFO
*) This field controls the RDA(Receive Data Available) flag or interrupt only, that is the actual
FIFO depth can’t be modified and fixed to 8. If this field is set to 1, it means that the RDA flag or
interrupt is influenced when the number of received data in the RX FIFO is 2. It is recommended
that this field is set to 0, so right after reception of some data, the RDA flag or interrupt can be
generated.
PR [3:2]
0
1
2, 3
Parity Bit Select
Even parity
Odd parity
Parity is disabled
9-6