TCC720 Datasheet, PDF (134/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
BOOTING PROCEDURE
Preliminary Spec 0.51
1 byte unit. (0xFF or others)
i) TCC720 enables UART as 9600 baud, none parity bit, 1 stop bit, and 7 data bits.
ii) It receives initial code size of 16bit.
iii) Receive a code of 32bit with order of MSB first and then 1 bit even parity information.
iv) If parity check is succeeded, TCC720 transfer an acknowledgement of 0xFF, or it
transfers 0x00, so a host must check if the transfer is succeeded or not.
v) After all of codes are transferred TCC720 branches to address 0x00000000.
This procedure is illustrated in figure 14.2.
Mode Setting
(9600 baud, None Parity, 1 Stop bit, 7 Data bits)
Receive the size of Initial Codes ( = SIZE)
consist of 16 consequtive bytes
transfer with MSB first order
Receive 1 word
Receive 1 bit of parity
Parity OK ?
Yes
Send ACK (= '0xff')
consist of 32 consequtive bytes
transfer with MSB first order
Parity is even, that is, if the
number of ones in the received
word is even, the parity bit is 0.
No
Send NACK (= '0x00')
Write the received code to SRAM
SIZE = SIZE - 4
No
SIZE == 0 ?
Yes
Jump to SRAM (0x00000000)
Figure 14.2 UART booting procedure
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