TCC720 Datasheet, PDF (77/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
USB CONTROLLER
Preliminary Spec 0.51
IN CSR1 Register (INCSR1n)
0x80000544
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
- CTGL STST ISST FLFF - FNE IRDY
CTGL [6]
1
Type
W
Clear Data Toggle Bit
The data toggle bit is cleared
STST [5]
1
0
Type
R
W
STALL Handshake Issued
Indicates that the STALL handshake is issued
Clear by writing 0
ISST [4]
1
0
FLFF [3]
1
0
FNE [1]
0
1
Type
R/W
R/W
Issue STALL Handshake
Start issuing a STALL Handshake
Clear to end STALL condition
Type
R/W
R
Issue FIFO Flush
IN FIFO is flushed
This bit is cleared by the USB when the FIFO is flushed. The
interrupt is generated when this happens. If a token is in
progress, the USB waits until the transmission is complete
before the FIFO is flushed. If two packets are loaded into the
FIFO, only the top-most packet (one that was intended to be
sent to the host) is flushed, and the corresponding IRDY bit for
that packet is cleared.
Type
R/W
R/W
IN FIFO Not Empty
Indicates that no packet of data is in IN-FIFO
Indicates that at least one packet of data is in IN-FIFO
IRDY [0]
0
1
Type
R
W
IN Packet Ready
Indicates that the packet has been successfully sent to host
After writing a packet of data into the IN-FIFO, set this bit to 1.
8-9