TCC720 Datasheet, PDF (56/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
CLOCK GENERATOR
Preliminary Spec 0.51
7.2 Register Description
Clock Generator Register Map (Base Address = 0x80000400)
Name
Address Type
Reset
Description
CKCTRL
0x00 R/W 0x0003FFE Clock Control Register
PLLMODE
0x04 R/W 0x03806 PLL Control Register
SCLKmode 0x08 R/W 0x082000 System Clock Control Register
DCLKmode 0x0C R/W 0x0800 DCLK (DAI/CODEC) Control Register
EXTCLKmode 0x14 R/W 0x0000 EXTCLK (CD/Other) Control Register
UTCLKmode 0x18 R/W 0x01BE UTCLK (UART) Control Register
UBCLKmode 0x1C R/W
0x00
UBCLK (USB) Control Register
TCLKmode 0x24 R/W
0x00
TCLK (Timer) Control Register
GCLKmode 0x28 R/W
0x00
GCLK (GSIO) Control Register
SW_nRST
0x3C R/W 0x3FFF Software Reset for each peripherals
Clock Control Register (CKCTRL)
0x80000400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PDN IDLE
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 XTIN PLL - GCK TCK - USB UART EXT - CDC DAI PCK
This controls various sources of clocks fed to each peripherals. If each control bit is set to 1, the
corresponding clock is disabled and the peripherals use that clock are also disabled. To enable the clock,
clear the control bit to 0.
Power down and Idle mode bit are write-only register, and it is always 0 when read CKCTRL register.
PDN [25]
1
Power Down Mode
TCC720 goes to power down mode. All blocks disabled.
IDLE [24]
1
Idle Mode
TCC720 goes to idle mode. Only ARM is disabled.
7-3