TCC720 Datasheet, PDF (126/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
The following figure displays the element cycle diagram for external memories.
SMEM_0 Type Cycle (Bus width >= Data width)
nCS
XA
nOE
tSH
nWE
DQ
ADDR0
tPW
tHLD
tSH
tH
DQ_R
ADDR1
tPW
DQ_W
tHLD
SMEM_0 Type Cycle (Bus width < Data width)
nCS
XA
nOE
tSH
ADDR0
tPW
tHLD
tH
DQ
DQ_RL
ADDR1
tPW
DQ_RH
SMEM_1 Type Cycle (Bus width >= Data width)
nCS
XA
nOE
tSH
nWE
DQM1
ADDR0
tPW
tHLD
tSH
tH
DQM0
DQ[15:8]
DQ[7:0]
DQ₀
ADDR1
tPW
Figure 13.3 Basic Timing Diagram for External Memories
tHLD
DQ₁
In case of IDE type memories, there are two chip enable signals for it. In TCC720, each enable
can be controlled by offset address space. ‘nCS0’ reflects that the offset address range of 0 ~
0x1F is accessed, ‘nCS1’ reflects that 0x20 ~ 0x3F is accessed. For larger address than 0x3F, if
bit5 of address value means which enable signal is activated. (0 to ‘nCS0’, 1 to ‘nCS1’)
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