TCC720 Datasheet, PDF (59/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
CLOCK GENERATOR
Preliminary Spec 0.51
System Clock Control Register (SCLKmode)
0x80000408
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
PS XTI
P_PHASE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HS 0
H_PHASE
00
F_PHASE
It generates FCLK, HCLK, PCLK for system operation. FCLK is dedicated for ARM940T
processor, HCLK is used as internal AHB bus clock, and PCLK is for APB bus clock. Each clock
is generated by 6bit DCO (Digital Controlled Oscillator) that can generate a stable and variable
frequency as long as its frequency is below about 0.1 times of that of divisor clock. For reliable
operation, keep the n power of 2 relationships with divisor clock.
The target frequency can be acquired by writing the phase value calculated by the following
equation to the PHASE register.
PHASE = 2⁶ * f_SCLK / f_DIV
PS,XTI [23:22]
PCLK Clock Select
00
use DIVCLK1 as a divisor clock of PCLK generator
01
use XTIN pin as a divisor clock of PCLK generator
1x
use FCLK as a divisor clock of PCLK generator
P_PHASE [21:16]
n (!= 0)
f_PCLK = f_DIV * n / 2⁶
PCLK Frequency Select
0
f_PCLK = f_DIV or f_XTIN (depends on PS, XTI bit)
*) The DIVCLK1 is selected by DIV1 bit of PLLmode register.
HS [15]
HCLK Clock Select
0
use DIVCLK1 as a divisor clock of HCLK generator
1
use FCLK as a divisor clock of HCLK generator
H_PHASE [13:8]
HCLK Frequency Select
n (!= 0)
f_HCLK = f_DIV * n / 2⁶
0
f_PCLK = f_DIV or f_FCLK (depends on HS bit)
F_PHASE [5:0]
n (!= 0)
0
f_FCLK = f_DIV * n / 2⁶
f_PCLK = f_DIV
FCLK Frequency Select
7-6