TCC720 Datasheet, PDF (20/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
Analog Interface & ETC Register Map (Base Address = 0x80000A00)
Name Address Type
Reset
Description
ADCTR 0x00 R/W
ADDATA 0x04
R
CDCTR 0x08 R/W
CDCGAIN 0x0C R/W
LZC
0x10 R/W
USBCTR 0x14 R/W
TSTSEL 0x18 R/W
0
ADC Control Register
-
ADC Data Register
0
Codec Control Register
0
Codec Gain Register
-
Leading Zero Counter Register
0
USB Port Control Register
0
Test Mode Register (must be remained zero)
DMA Controller Register Map (Base Address = 0x80000E00)
Name Address Type
Reset
Description
ST_SADR 0x00
R/W
-
Start Address of Source Block
SPARAM 0x04/0x08 R/W
-
Parameter of Source Block
C_SADR 0x0C
R
-
Current Address of Source Block
ST_DADR 0x10
R/W
-
Start Address of Destination Block
DPARAM 0x14/0x18 R/W
-
Parameter of Destination Block
C_DADR 0x1C
R
-
Current Address of Destination Block
HCOUNT 0x20
R/W 0x00000000 Initial and Current Hop count
CHCTRL
0x24
R/W 0x00000000 Channel Configuration
Memory Controller Register Map (Base Address = 0xF0000000)
Name Address Type
Reset
Description
SDCFG 0x00 R/W 0x4268A020 SDRAM Configuration Register
SDFSM 0x04
R
-
SDRAM FSM Status Register
MCFG
0x08 R/W 0xZZZZ_02 Miscellaneous Configuration Register
TST
0x0C
W
0x0000 Test mode register (must be remained zero)
CSCFG0
0x10
R/W
External Chip Select 0 Configuration
0x0B405601
Register (Initially set to SRAM)
CSCFG1
0x14
R/W
External Chip Select 1 Configuration
0x0150569A
Register (Initially set to IDE)
CSCFG2
0x18
R/W
External Chip Select 2 Configuration
0x0060569A
Register (Initially set to NAND)
CSCFG3
0x1C
R/W
External Chip Select 3 Configuration
0x0A70569A
Register (Initially set to NOR)
2-8