TCC720 Datasheet, PDF (119/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
SDBASE [27:24]
SDRAM Base Address
N
Indicates the MSB 4bit of SDRAM area. That is SDRAM base = 0xN0000000
RC [23:21]
Delay of Refresh to Idle (tRC)
n
n number of HCLK cycle is used to meet the refresh to idle delay time
RCD [20:18]
Delay of RAS to CAS (tRCD)
n
(n+1) number of HCLK cycle is used to meet the RAS to CAS delay time
RD [17:15]
n
Delay of Read to Precharge (tRD)
n number of HCLK cycle is used to meet the read to precharge time
RP [14:12]
n
Delay of Precharge to Refresh (tRP)
(n+1) number of HCLK cycle is used to meet the precharge to refresh time
RW [11]
0
1
RAS Width
12bit is used for RAS address bus
13bit is used for RAS address bus
Refresh [10:0]
Refresh Cycle
n
Every (n * 16 + 15) number of HCLK cycle has passed, the SDRAM refresh
request is generated. If on going cycle has finished, the refresh cycle starts.
Real refresh period depends on the period of HCLK.
SDRAM FSM Status Register (SDFSM)
31 30 29 28 27 26 25 24 23 22 21 20 19
0
15 14 13 12 11 10 9 8 7 6 5 4 3
0
SDFSM
*) Represents current status of finite state machine in the SDRAM controller.
0xF0000004
18 17 16
210
13 - 4