TCC720 Datasheet, PDF (62/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
CLOCK GENERATOR
Preliminary Spec 0.51
UTCLK (UART) Control Register (UTCLKmode)
0x80000418
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVUT
UT_PHASE[13:0]
DIVUT [15:14]
0
1
2, 3
UTCLK Divisor Clock Select
use XIN pin as a divisor clock of UTCLK generator
use PLL output as a divisor clock of UTCLK generator
use XTIN pin as a divisor clock of UTCLK generator
UT_PHASE [13:0]
UTCLK Clock Frequency Select
u (!= 0)
f_UTCLK = f_DIV * u / 2¹⁴
0
f_UTCLK = f_DIV
*) The divisor clock is selected by DIVUT bit of UTCLKmode. UTCLK is also controlled by UART bit of
CKCTRL register that can enable or disable UTCLK. If this bit is set to high, UTCLK is disabled and if it is
low, UTCLK is enabled
This clock is used by UART. For reliable communication with host side, this clock has the
frequency of 3.6864MHz or so. The UART clock is then divided by DL register in UART block, it
is not so important to maintain the duty ratio of 50%.
7-9