TCC720 Datasheet, PDF (113/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
DMA CONTROLLER
Preliminary Spec 0.51
Channel Control Register (CHCTRL)
31 30 29 28 27 26 25 24
0
15 14 13 12 11 10 9 8
CONT
PRI
LOCK
TYPE
0x80000E24
23 22 21 20 19 18 17 16
DMASEL[12:0]
76543210
BSIZE
WSIZE FLAG IEN REP EN
DMASEL [28:16]
non-zero
Select Source of DMA Request
Each bit field selects corresponding signal as a source for DMA request.
The bit-map of this register is identical with the IEN of interrupt controller.
So if you want to use EXINT0 pin as a source of DMA request, set
DMASEL[0] as 1 and select HW_ARBIT or HW_BURST type transfer.
If multiple bits of this register is set, all the corresponding signal can
generate DMA request for this channel.
CONT [15]
0
1
Issue Locked Transfer
DMA transfer begins from ST_SADR / ST_DADR address
DMA transfer begins from C_SADR / C_DADR address
It must be used after the former transfer has been executed, so that
C_SADR and C_DADR contains meaningful values.
PRI [14:12]
0
non-zero
Priority
Priority 0 is equal to disable DMA transfer
DMA channel is enabled only when have non-zero priority.
LOCK [11]
Issue Locked Transfer
0
DMA transfer executed without lock property
1
DMA transfer executed with lock property
*) Lock field controls the LOCK signal (refer to AHB specification), so that when the LOCK is set to 1, the
corresponding transfer doesn’t be bothered by other AHB masters like LCD controller, ARM etc. This field
is only meaningful for non-burst type of transfers.
TYPE [10:8]
Transfer Type
000
SINGLE transfer
001
HW_ARBIT transfer
101
HW_BURST transfer
010
SW_ARBIT transfer
110
SW_BURST transfer
*) Please refer to table 12.1 for detailed information of each transfer types.
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