TCC720 Datasheet, PDF (125/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
URDY [19]
1
Use Ready
Ready / Busy signal monitoring is enabled
The memory controller waits until the state of READY pin indicate that its
access request has accomplished.
RDY [18]
0
1
Ready / Busy Select
The selected GPIO pin indicating the READY signal.
The memory controller waits until this pin goes to high state.
The selected GPIO pin indicating the BUSY signal.
The memory controller waits until this pin goes to low state.
AMSK [14]
Address Mask Bit
0
Upper half of data bus is masked to zero.
*) In case of 16bit width NAND flash, the upper half byte must be held low, during address cycles. This bit
must be set to zero. But if the system uses multiple NAND flashes by sharing a chip select but separating
each data to 16 or 32bit data bus of TCC720, the AMSK must be set to 1, so the address can be fed to
each NAND flashes.
PSIZE [13:12]
psize
Page size of NAND Flash
The size of one page for NAND type flash.
It represents byte per page calculated by the following equation.
1 Page = 256 * 2^psize
CLADR [11:9]
N
Number of Cycle for Linear Address
The number of linear address command cycle for NAND type flash.
(N+1) cycle is used for generating linear address command.
STP [8:6]
N
Number of Cycle for Setup Time (tSH)
N cycle is issued between the falling edge of nCS[n] and nOE / nWE.
EPW,PW [5:3]
Number of Cycle for Pulse Width (tPW)
N ( = 0~15 ) (N+1) cycle is issued between the falling and rising edge of nOE / nWE.
HLD [2:0]
N
Number of Cycle for Hold Time (tHLD)
N cycle is issued between the rising edge of nOE / nWE and nCS[n].
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