TCC720 Datasheet, PDF (112/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
DMA CONTROLLER
Preliminary Spec 0.51
Current Source Address Register (C_SADR)
0x80000E0C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C_SADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C_SADR[15:0]
*) This register contains current source address of DMA transfer.
Current Destination Address Register (C_DADR)
0x80000E1C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C_DADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C_DADR[15:0]
*) This register contains current destination address of DMA transfer.
HOP Count Register (HCOUNT)
0x80000E20
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C_HCOUNT[15:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_HCOUNT[15:0]
C_HCOUNT [31:16]
Current Hop Count
cn
Represent cn number of Hop transfer remains
ST_HCOUNT [15:0]
Start Hop Count
sn
Represent sn number of Hop transfer is transferred.
*) At the beginning of transfer, the C_HCOUNT is stored by ST_HCOUNT register. And at the
end of every hop transfer, this is decremented by 1 until reached to 0.
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