TCC720 Datasheet, PDF (117/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
Memory Controller Register Map (Base Address = 0xF0000000)
Name Address Type
Reset
Description
SDCFG 0x00 R/W 0x4268A020 SDRAM Configuration Register
SDFSM 0x04
R
-
SDRAM FSM Status Register
MCFG
0x08 R/W 0xZZZZ_02 Miscellaneous Configuration Register
TST
0x0C
W
0x0000 Test mode register (must be remained zero)
CSCFG0
0x10
External Chip Select 0 Configuration
R/W 0x0B405601
Register (Initially set to SRAM)
CSCFG1
0x14
External Chip Select 1 Configuration
R/W 0x0150569A
Register (Initially set to IDE)
CSCFG2
0x18
External Chip Select 2 Configuration
R/W 0x0060569A
Register (Initially set to NAND)
NAND flash Register Map (Base Address = N * 0x10000000)
Name Address Type
Reset
Description
CMD
0x00 R/W
-
Command Cycle Register
LADDR
0x04
W
-
Linear Address Cycle Register
BADDR
0x08
W
-
Block Address Cycle Register
IADDR
0x0C
W
-
Single Address Cycle Register
DATA
0x10 R/W
-
Data Access Cycle Register
*) N represents BASE field of CSCFGn registers.
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