TCC720 Datasheet, PDF (35/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
INTERRUPT CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
4.2 Register Description
Interrupt Controller Register Map (Base Address = 0x80000100)
Name Address Type
Reset
Description
IEN
0x00 R/W 0x0000 Interrupt Enable Register
CREQ
0x04
W
-
Clear Interrupt Request Register
IREQ
0x08
R
0x0000 Interrupt Request Flag Register
IRQSEL 0x0C R/W 0x0000 IRQ/FIQ Select Register
ICFG
0x10 R/W 0x0000 External Interrupt Configuration Register
MREQ
0x14
R
0x0000 Masked Interrupt Request Flag Register
TSTREQ 0x18 R/W 0x0000 Test Mode Register (must be remained zero)
Interrupt Enable Register (IEN)
0x80000100
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEN - DMA LCD CDIF - GS UB UT TC I2T I2R E3 E2 E1 E0
MEN [15]
0
1
Master Enable
All interrupts are disabled
All interrupt enabled by corresponding bit[14:0] can be passed to CPU
Bit Field
DMA _[13]
LCD _[12]
CDIF _[11]
[10]
GS _[9]
UB _[8]
UT _[7]
TC _[6]
I2T _[5]
I2R _[4]
E3 _[3]
E2 _[2]
Each Interrupt Request Control
1 = Interrupt enabled, 0 = Interrupt disabled
DMA interrupt control
LCD interrupt control
CDIF interrupt control
Not used
GSIO interrupt control
USB interrupt control
UART/IrDA interrupt control
Timer/Counter interrupt control
I2S TX interrupt control
I2S RX interrupt control
External interrupt request 3 control
External interrupt request 2 control
4-2