TCC720 Datasheet, PDF (44/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
TIMER / COUNTER
Preliminary Spec 0.51
Watchdog Timer Configuration Register (TWDCFG)
0x80000270
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
TCKSEL
IEN 0 RST EN
Watchdog timer is used for the system not to be stuck by generating a reset pulse automatically
when the watchdog timer counter overflows to zero.
The programmer must clear the watchdog counter before it overflows by writing any value to
TWDCLR register.
TCKSEL [6:4]
TCK Select
k=0~4
TCK is internally generated from divider circuit. It is driven by PCLK, and this
value determines the division factor of this circuit. Division factor is 2^(k+1).
k = 5, 6
TCK is internally generated from divider circuit. It is driven by PCLK, and this
value determines the division factor of this circuit. Division factor is 2^2k
k=7
Undefined. Should not be used.
IEN [3]
1
Interrupt Enable
Watchdog Timer Interrupt is initiated.
This field is valid only if RST field is set to 0.
RST [1]
0
1
Reset Enable
Watchdog timer does not generate reset signal although it reaches to the
reference value, and it continue counting from 0.
Watchdog timer generates the reset signal when it reaches to the reference
value, the reset signal is applied to every component in the chip.
EN [0]
1
Watchdog Timer Enable
Watchdog timer is enabled. If the watchdog timer is disabled, its counter
goes to 0xffe0, so when it is first enabled, user must clear the counter by
writing to TWDCLR register.
Watchdog Timer Clear Register (TWDCLR)
0x80000274
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
any value
*) The watchdog timer counter can be cleared to 0 by writing any value to this register. If it is not
cleared before it overflows, the watchdog timer generate reset signal to the entire component of
chip.
5-6