TCC720 Datasheet, PDF (75/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
USB CONTROLLER
Preliminary Spec 0.51
Endpoint Interrupt Enable Register (UBEIEN)
0x8000051C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
- - - - - EP2 EP1 EP0
USB Interrupt Enable Register (UBIEN)
0x8000052C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
- - - - - RST RSM SP
Corresponding to each interrupt register, there is an INTERRUPT ENABLE register (except resume
interrupt enable). By default, the USB reset interrupt is enabled.
If bit = 0, the interrupt is disabled.
If bit = 1, the interrupt is enabled.
Frame Number 1 Register (UBFRM1)
0x80000530
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FRM1
Frame Number 2 Register (UBFRM2)
0x80000534
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FRM2
There are two registers, UBFRM1 and UBFRM2, which inform the frame number received from
the host. The UBFRM1 denotes the lower byte of frame number. The UBFRM2 denotes the
higher byte of frame number.
Frame number = [UBFRM2[7:0] : UBFRM1[7:0]]
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