TCC720 Datasheet, PDF (111/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
DMA CONTROLLER
Preliminary Spec 0.51
Destination Block Parameter Register (DPARAM)
31 30 29 28 27 26 25 24 23 22
DMASK[23:8]
15 14 13 12 11 10 9 8 7 6
DMASK[7:0]
0x80000E14 / 0x80000E18
21 20 19 18 17 16
543210
DINC[7:0]
DMASK [23:8]
Destination Address Mask Register
0
non-masked
1
masked
*) Each bit field controls the corresponding bit of source address field. That is, if DMASK[23] is
set to 1, the 28th bit of source address is masked, and if DMASK[22] is set to 1, the 27th bit of
source address is masked, and so on. If a bit is masked, a corresponding bit of address bus is
unchanged during DMA transfer. This function can be used to generate circular buffer address.
DINC [7:0]
dinc
Destination Address Increment Register
Destination address is added by amount of dinc at every write cycles. dinc
is represented as 2’s complement, so if DINC[7] is 1, the destination
address is decremented.
The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected
during DMA transfer. If the source or destination address reaches its maximum address space
like 0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000
not from 0x80000000 or 0x30000000.
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