TCC720 Datasheet, PDF (114/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
DMA CONTROLLER
Preliminary Spec 0.51
BSIZE [7:6]
0
1
2, 3
Burst Size
1 Hop transfer consists of 1 pair of read and write cycle.
1 Hop transfer consists of 2 pair of read and write cycle
1 Hop transfer consists of 4 pair of read and write cycle
WSIZE [5:4]
0
1
2, 3
Word Size
byte transfer
half word transfer
word transfer
FLAG [3]
1
DMA Flag
Represents that all hop of transfers are fulfilled
IEN [2]
Interrupt Enable
1
At the same time FLAG goes to 1, DMA interrupt request is generated.
*) To generate IRQ or FIQ interrupt, the corresponding enable bit in the interrupt controller must be set to 1
ahead.
CONT [1]
Continuous Transfer
0
After all of hop transfer has executed, the DMA channel is disabled
The DMA channel remains enabled, so when another DMA request has
1
occurred, the DMA channel start transfer data again with the same manner
(type, address, increment, mask) as the latest transfer of that channel.
*) This bit is only valid if the transfer type is hardware and non-burst type transfer.
EN [0]
0
1
DMA Channel Enable
DMA channel is disabled or terminated.
Once terminated, user must make HCOUNT to 0 not to continue transfer
after channel is re-enabled.
DMA channel is enabled. If software type transfer is selected, this bit
generates DMA request directly, or if hardware type transfer is used, the
interrupt request generates DMA request.
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