TCC720 Datasheet, PDF (118/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
13.2 SDRAM Controller
SDRAM controller can control from 64Mbit up to 256Mbit SDRAM. In TCC720 system, the
SDRAM contains almost parts for system operation. (program, data, ESP buffer, etc is located in
SDRAM).
The SDRAM parameter such as size, refresh period, RAS to CAS delay, refresh to idle delay
can be programmed by internal register.
The registers for SDRAM controller is as the followings.
Refer to SDRAM cycle diagram in figure 13.2
SDRAM Configuration Register (SDCFG)
0xF0000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CL BW
CW
SDBASE
RC
RCD
RD[2:1]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD0
RP
RW
Refresh
*) The reset value means the following configuration.
CL=2cycle, CW=8bit, BW=16bit, SDBASE=2, RC =3, RCD=2, RD=1, RP=2, RW=12bit, Refresh=0x20
CL [31]
0
1
CAS latency is 2 cycle
CAS latency is 3 cycle
CAS Latency (tCL)
BW [30]
0
1
Bus Width Select
Bus width for SDRAM is 32 bit
Bus width for SDRAM is 16 bit
CW [29:28]
0, 1
2
3
CAS Width
8 bit is used for CAS address
9 bit is used for CAS address
10 bit is used for CAS address
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