TCC720 Datasheet, PDF (128/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
Single Address Cycle Register (IADDR)
31 30 29 28 27 26 25 24 23 22 21 20 19
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3
Reserved
IADDR
*) When CPU writes to this register, one cycle of address cycle is generated.
0xM000000C
18 17 16
210
Data Register (DATA)
0xM0000010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA3
DATA2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
DATA0
*) DATA3~1 may be used as the value of data register, otherwise only DATA0 is used as data register. The
number of data cycle is dependent on the bus width of NAND flash and the data size of access cycle.
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