TCC720 Datasheet, PDF (55/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
CLOCK GENERATOR
Preliminary Spec 0.51
WAITGEN cell is for waiting until oscillation is stabilized. It blocks internal clocks until about
2^18 number of XIN transition occurs after reset is released. If frequency of XIN is 16MHz, the
wait time is about 16.4 ms
The DIVCLK1 are used as main clock of TCC720 and it can be either an oscillator output or PLL
output clock. It is the source of system clocks (FCLK, HCLK, PCLK). The PCLK can be also
driven by XTIN. The other clocks each can be driven by one of 3 clock sources XIN, PLLOUT,
XTIN independently by its mode register.
DCO Control
DCLK is used as the master clock of DAI (Digital Audio Interface) block when it’s mode is set to
master mode. EXTCLK is used for external usage especially for CD application. UTCLK is used
as the main clock of UART controller.
These clocks are generated by 14bit DCO (Digital Controlled Oscillator) that can generate a
stable and variable frequency as long as its frequency is below about one tenth of the divisor
clock. For reliable operation of DAI, divisor clock frequency must be higher than about 200
MHz. But maximum frequency of ARM940T is lower than 120MHz, the division factor for FCLK
must be greater than 2.
The target frequency can be acquired by writing the phase value calculated by the following
equation to the each PHASE register.
D_PHASE = 2¹⁴ * f_DCLK / f_DIV
CV_PHASE = 2¹⁴ * f_CVCLK / f_DIV
EXT_PHASE = 2¹⁴ * f_EXTCLK / f_DIV
UT_PHASE = 2¹⁴ * f_UTCLK / f_DIV
For example, when you use 44.1KHz sampling rate and want to set DCLK as 256fs, the target
frequency of DCLK is 256 * 44.1k = 11.2896 MHz, and if you set PLL to 266MHz, the D_PHASE
value must be set to 696 ( ~= 2¹⁴ * 11.2896 / 266).
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