TCC720 Datasheet, PDF (127/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
In case of NAND flash type memories, there are several sub-registers for accessing.
The followings are these sub-registers. (M is base field of CSCFGn register)
Command Cycle Register (CMD)
0xM0000000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMD3
CMD2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD1
CMD0
*) If bus width of NAND flash is more than 8bit, the CMD1 ~ 3 may be used as command register,
otherwise only CMD0 is used as command register. The following values are an example commands for
NAND flash of SAMSUNG.
0x00/0x01 : Page Read Command
0x50 : Spare Read Command
0x80 : Page Program Command
0x60 : Block Erase Command
0x70 : Status Read Command
(status read command is generated by reading 0xM0000700 address, not 0xM0000000)
*) Refer to corresponding datasheet of NAND flash chip for detailed command list.
Linear Address Cycle Register (LADDR)
0xM0000004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LADDR[15:0]
*) LADDR is used as the linear address for accessing NAND flash data. The number of cycle is
determined by CLADR of CSCFGn register. Memory controller assumes that the byte per page
is 512, so from the second cycle of address, LADDR[31:9] value is fed to NAND flash.
Block Address Cycle Register (BADDR)
0xM0000008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BADDR[15:0]
*) BADDR is used as the block address for accessing NAND flash data with a block unit. The
number of cycle is determined by CLADR and PSIZE of CSCFGn register.
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