TCC720 Datasheet, PDF (109/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
DMA CONTROLLER
Preliminary Spec 0.51
12.2 Register Description
DMA Controller Register Map (Base Address = 0x80000E00)
Name Address Type
Reset
Description
ST_SADR 0x00
R/W
-
Start Address of Source Block
SPARAM 0x04/0x08 R/W
-
Parameter of Source Block
C_SADR 0x0C
R
-
Current Address of Source Block
ST_DADR 0x10
R/W
-
Start Address of Destination Block
DPARAM 0x14/0x18 R/W
-
Parameter of Destination Block
C_DADR 0x1C
R
-
Current Address of Destination Block
HCOUNT 0x20
R/W 0x00000000 Initial and Current Hop count
CHCTRL
0x24
R/W 0x00000000 Channel Configuration
CLRDRQ 0x28
W
-
Clear End of DMA flag
Start Source Address Register (ST_SADR)
0x80000E00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST_SADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_SADR[15:0]
*) This register contains the start address of source block for DMA transfer. The transfer begins
reading data from this address.
Start Destination Address Register (ST_DADR)
0x80000E10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST_DADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_DADR[15:0]
*) This register contains the start address of destination block for DMA transfer.
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