TCC720 Datasheet, PDF (74/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
USB CONTROLLER
Preliminary Spec 0.51
The EP0 interrupt is generated under the following conditions:
1. OUT Packet is ready. ORDY field is set in the CSR register
2. IN Packet is ready. IRDY field is set in the CSR register
3. SENT STALL is set
4. SETUP END is set
5. DATA END is cleared (End of control transfer)
The EP1/E2 interrupt is generated under the following conditions:
For IN endpoints
1. IRDY field is cleared in the CSR register
2. FIFO is flushed
3. SENT STALL is set
For OUT endpoints
1. ORDY field is set in the CSR register.
2. SENT STALL is set
The suspend interrupt is generated when the USB receives suspend signaling. The SP bit field of the
UBIR is set whenever there is no activity for 3ms on the bus. This interrupt is disabled in default. The
resume interrupt is generated by a USB reset in suspend mode. The USB reset interrupt is generated
when USB controller receives the reset signaling from the host.
8-6