TCC720 Datasheet, PDF (129/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
14.5 Internal Memories
In TCC720, there is 64Kbytes of SRAM for general purposes and 4Kbytes of ROM for system
initialization. SRAM area is dedicated to area 3 (0x30000000 ~ 0x3FFFFFFF), and also
accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when there are no devices assigned to area
0. ROM area is dedicated to area E (0xE0000000 ~ 0xEFFFFFFF), and also accessed by area
0 (0x00000000 ~ 0x0FFFFFFF) when RM flag of MCFG register is cleared to 0.
In case of internal ROM, the access speed is not enough to cope with that of system bus (AHB).
So when the system bus clock is higher than about 40MHz, the ROM access cycle must be
extended by inserting 1 wait cycle. This wait cycle is determined by writing any value to ROM
area.
When writing to address the bit 2 of which is 1 (such as 0xE0000004, 0xE000000C,
0xE0000014, …) , the wait cycle is to be inserted from the next ROM access cycle. On the other
hand writing to address the bit 2 of which is 0 (such as 0xE0000000, 0xE0000008, 0xE0000010,
…), the wait cycle is to be removed from the next ROM access cycle.
The access time of internal SRAM is faster than that of internal ROM, so there is no need to
extend access cycle for SRAM.
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