TCC720 Datasheet, PDF (78/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
USB CONTROLLER
Preliminary Spec 0.51
EP0 CSR Register (EP0CSR)
0x80000544
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CLSE CLOR ISST CEND DEND STAL IRDY ORDY
*) EP0 CSR register can access by writing “0” to UBIDX register, and use same address as INCSR1.
CLSE [7]
1
Type
W
Clear Setup End Bit
The SEND bit is cleared
CLOR [6]
1
Type
W
Clear Output Packet Ready Bit
The ORDY bit is cleared
ISST [5]
1
0
Type
R/W
W
Issue STALL Handshake
Start issuing a STALL Handshake. At the same time, it clears
ORDY bit if it decodes an invalid token
End the STALL condition
CEND [4]
1
0
Type
R
R
Control Setup End
Indicates that the control transfer ends before DEND bit is set
Indicates that the CLSE is written by “1”.
At the same time, the USB flushes the FIFO, and invalidates
access to the FIFO. That is, when the access to the FIFO is
invalidated, this bit is cleared.
DEND [3]
1
Type
R
Data End
Indicates that the one of the following conditions matched.
- after loading the last packet of data into the FIFO.
(at the same time IRDY is set)
- while it clears ORDY after unloading the last packet of data.
- for a zero length data phase
(at the same time, it clears ORDY and sets IRDY)
STAL [2]
1
Type
R
IN Packet Ready
Indicates that a control transaction is ended due to a protocol
violation
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