TCC720 Datasheet, PDF (108/143 Pages) List of Unclassifed Manufacturers – 32-bit RISC Microprocessor For Digital Media Player

TCC720
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
DMA CONTROLLER
Preliminary Spec 0.51
In SINGLE type transfer, 1 Hop of transfer occurs only once at every DMA requests. The 1 Hop of
transfer means 1 burst read followed by 1 burst write. 1 burst means 1, 2 or 4 consecutive read or write
cycles defined by CHCTRL[7:6] field.
Hardware type transfer (HW_ARBIT, HW_BURST) means that the DMA transfer triggered by external or
internal hardware blocks selected by CHCTRL[28:16] field. This field has same mapping with interrupt
enable flag of interrupt controller, so the DMA transfer can be occurred as like as interrupt is generated.
Software type transfer (SW_ARBIT, SW_BURST) means that the DMA transfer triggered by CHCTRL[0]
flag (enable flag). When this flag is set to 1, the DMA transfer begins at the same time.
Arbitration type transfer (HW_ARBIT, SW_ARBIT) means that at the end of every HOP transfer, the AHB
bus is released from DMA channel so other master can occupy the bus when the master has requested
the bus.
Burst type transfer (HW_BURST, SW_BURST) means that once the DMA transfer occurs, all of transfers
are executed without further DMA requests.
Lock field controls the LOCK signal (refer to AHB specification), so that when the LOCK is set to 1, the
corresponding transfer doesn’t be bothered by other AHB masters like LCD controller, ARM etc. This field
is only meaningful for non-burst type of transfers.
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