DS80C320-MCG Datasheet, PDF (99/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
INTERNAL TIMING RELATIONSHIPS IN PMM1 Figure 7-2
SINGLE-CYCLE INSTRUCTION
SINGLE-CYCLE
INSTRUCTION
MACHINE
CYCLES
MACHINE CYCLE
MACHINE CYCLE
C1
C2
C3
C4
C1
C2
ALE
INTERNAL
CLOCK
(PMM1)
EXTERNAL
CLOCK
64 CLOCK CYCLES
PMM1 and PMM2 are entered and exited by setting the Clock Rate Divider bits (PMR.7-6). In addition, it
is possible use the switchback feature to effect a return to the divide by 4 mode from either power
management mode. This allows both hardware and software to cause an exit from PMM. Entry to or exit
from either PMM must be by the divide by 4 mode. This means that to switch from divide by 64 to
divide by 1024 and vice versa, one must first switch back to divide by 4 mode. Attempts to execute an
illegal speed change will be ignored and the bits will remain unchanged. It is the responsibility of the
software to test for serial port activity before attempting to change speed, as a modification of the clock
divider bits during a serial port operation will corrupt the data.
PMM AND PERIPHERAL FUNCTIONS
Timers 0, 1, and 2 will default on reset to a 12 clock per cycle operation to remain compatible with the
original 8051 timing. The timers can be individually configured to run at machine cycle timing (divide
by 4) by setting the relevant bits in the Clock Control Register (CKCON;8Eh). Because the timers derive
their time base from the internal clock, timers 0, 1, and 2 operate at reduced clock rates during PMM.
This will also affect the operation of the serial ports in PMM. In general, it is not possible to generate
standard baud rates while in PMM, and the user is advised to avoid PMM or use the switchback feature if
serial port operation is desired. Table 7-4 shows the effect of the clock divider value on timer operation.
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