DS80C320-MCG Datasheet, PDF (147/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
The RXD signal is used for both transmission and reception. TXD provides the shift clock. Data bits
enter and exit LSb first. The baud rate is equal to the shift clock frequency. This can be either oscillator
divided by 4 or oscillator divided by 12. The relevant UART will begin transmitting when any
instruction writes to SBUF0 or SBUF1 (hex address 99 or C1). The internal shift register will then begin
to shift data out. The clock will be activated and will transfer data until the 8-bit value is complete. Data
will be presented one oscillator cycle prior to the falling edge of the shift clock (TXD), and an external
device can latch the data using the rising edge.
The UART will begin to receive data when the REN bit in the SCON register (SCON0.4 or SCON1.4) is
set to a logic 1 and the RI bit (SCON0.0 SCON1.0) is set to a logic 0. This condition tells the UART that
there is data to be shifted in. The shift clock (TXD) will activate and the UART will latch incoming data
on the rising edge. The external device should therefore present data on the falling edge. This process
will continue until 8 bits have been received. The RI bit will automatically be set to a logic 1, one
machine cycle following the last rising edge of the shift clock on TXD. This will cause reception to stop
until the SBUF has been read, and the RI bit cleared. When RI is cleared, another byte will be shifted in.
Mode 1
This mode is asynchronous, full duplex, using a total of 10 bits. The 10 bits consist of a start bit (logic 0),
8 data bits, and 1 stop bit (logic 1) as illustrated in Figure 12-2. The data is transferred LSb first. As
described above, the baud rates for Mode 1 are generated by either a divide by 16 of Timer 1 rollover, a
divide by 16 of the Timer 2 rollover, or a divide by 16 of (Timer 1 rollover)/2. The UART will begin
transmission 5 oscillator cycles after the first rollover of the divide by 16 counter following a software
write to SBUF. Transmission takes place on the TXD pin. It begins by the start bit being placed on the
pin. Data is then shifted out onto the pin, LSb first. The stop bit follows. The TI bit is set two oscillator
cycles after the stop bit is placed on the pin. All bits are shifted out at the rate determined by the baud
rate generator.
Once the baud rate generator is active, reception can begin at any time. The REN bit (SCON0.4 or
SCON1.4) must be set to a logic 1 to allow reception. The falling edge of a start bit on the RXD pin will
begin the reception process. Data will be shifted in at the selected baud rate. At the middle of the stop bit
time, certain conditions must be met to load SBUF with the received data:
1. RI must = 0, and either
2. If SM2 = 0, the state of the stop bit doesn’t matter, or
3. If SM2 = 1, the state of the stop bit must=1.
If these conditions are true, then SBUF (hex address 99h or C1h) will be loaded with the received byte,
the RB8 bit (SCON0.2 or SCON1.2) will be loaded with the stop bit, and the RI bit (SCON0.0 or
SCON1.0) will be set. If these conditions are false, then the received data will be lost (SBUF and RB8
not loaded) and RI will not be set. Regardless of the receive word status, after the middle of the stop bit
time, the receiver will go back to looking for a 1 to 0 transition on the RXD pin.
Each data bit received is sampled on the 7^th, 8^th and 9^th clock used by the divide by 16 counter. Using
majority voting, two equal samples out of the three, determines the logic level for each received bit. If
the start bit was determined to be invalid (=1), then the receiver goes back to looking for a 1 to 0
transition on the RXD pin in order to start the reception of data.
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