DS80C320-MCG Datasheet, PDF (136/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
The Watchdog time-out selection is made using bits WD1 (CKCON.7) and WD0 (CKCON.6) as shown
in the figure. The time-out selections possible are shown in the bit descriptions that follow. The
watchdog timeout period is affected by the use of Power Management modes. The slower clock rate,
either divide by 64 or divide by 1024 is used as the input source for the watchdog timer. This allows the
watchdog period to remain synchronized with device operation.
As discussed above, the Watchdog Timer has several SFR bits that contribute to its operation. It can be
enabled to function as either a reset source, interrupt source, software polled timer or any combination of
the three. Both the reset and interrupt have status flags. The Watchdog also has a bit that restarts the
timer. A summary table showing the bit locations is below. A description follows.
BIT NAME
EWT
RWT
WD1
WD0
WTRF
EWDI
WDIF
DESCRIPTION
Enable Watchdog Timer Reset
Reset Watchdog Timer
Watchdog interval 1
Watchdog interval 0
Watchdog Timer Reset Flag
Enable Watchdog Timer Interrupt
Watchdog Interrupt Flag
REGISTER LOCATION
WDCON – D8h
WDCON – D8h
CKCON – 8Eh
CKCON – 8Eh
WDCON – D8h
EIE – E8h
WDCON – D8h
BIT POSITION
WDCON.1
WDCON.0
CKCON.7
CKCON.6
WDCON.2
EIE.4
WDCON.3
The Watchdog Timer is a free running timer. It will be disabled by a Power-fail Reset. A Watchdog
time-out reset will not disable the Watchdog Timer, but will restart the timer. In general, software should
set the Watchdog to whichever state is desired, just to be certain of its state. Control bits that support
Watchdog operation are described below.
WDCON REGISTER SUMMARY
WATCHDOG CONTROL WDCON; D8h
WDCON.3
WDCON.2
WDIF - Watchdog Interrupt Flag. If the Watchdog Interrupt is
enabled (EIE.4), hardware will set this bit to indicate that the
Watchdog Interrupt has occurred. If the interrupt is not enabled,
this bit indicates that the time-out has passed. If the Watchdog
Reset is enabled (WDCON.1), the user has 512 clocks to strobe the
Watchdog prior to a reset. Software or any reset can clear this flag.
WTRF - Watchdog Timer Reset Flag. Hardware will set this bit
when the Watchdog Timer causes a reset. Software can read it, but
must clear it manually. A Power-fail Reset will also clear the bit.
This bit assists software in determining the cause of a reset. If
EWT=0, the Watchdog Timer will have no affect on this bit.
WDCON.1
EWT - Enable Watchdog Timer Reset. Setting this bit will turn on
the Watchdog Timer Reset function. The interrupt will not occur
unless the EWDI bit in the EIE register is set. A reset will occur
according to the WD1 and WD0 bits in the CKCON register.
Setting this bit to a 0 will disable the reset but leave the timer
running.
136 of 175