DS80C320-MCG Datasheet, PDF (44/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

Status Register (STATUS)
7
6
5
SFR C5
PIP
HIP
LIP
R-0
R-0
R-0
High-Speed Microcontroller User’s Guide
4
XTUP
R-0*
3
SPTA1
R-0
2
SPRA1
R-0
1
SPTA0
R-0
0
SPRA0
R-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, *=See description
PIP
Bit 7
HP
Bit 6
LIP
Bit 5
XTUP
Bit 4
SPTA1
Bit 3
SPRA1
Bit 2
SPTA0
Bit 1
SPRA0
Bit 0
Power Fail Priority Interrupt Status. When set, this bit indicates that software
is currently servicing a power-fail interrupt. It is cleared when the program
executes the corresponding RETI instruction. This bit is indeterminate on
devices which do not incorporate the power-fail interrupt.
High Priority Interrupt Status. When set, this bit indicates that software is
currently servicing a high priority interrupt. It is cleared when the program
executes the corresponding RETI instruction.
Low Priority Interrupt Status. When set, this bit indicates that software is
currently servicing a low priority interrupt. It is cleared when the program
executes the corresponding RETI instruction.
Crystal Oscillator Warm-up Status. This bit indicates whether the CPU
crystal oscillator has completed the 65,536 cycle warm-up and is ready to
operate from the external crystal or oscillator. This bit is cleared each time the
crystal oscillator is restarted following an exit from Stop mode or the XTOFF bit
(PMR.3) is set. While cleared, this bit prevents software from setting the XT/ RG
bit (EXIF.3) to enable operation from the crystal. Note that XTUP differs from
the RGMD bit (EXIF.2) in that XTUP shows the status of the crystal while
RGMD shows the current clock source. This bit is set to 1 following a power–on
reset, but is unaffected by other forms of reset.
Serial Port 1 Transmit Activity Monitor. When set, this bit indicates that data
is currently being transmitted by serial port 1. It is cleared when the internal
hardware sets the TI_1 bit. Do not alter the Clock Divide Control bits (PMR.7-6)
while this bit is set or serial port data may be lost.
Serial Port 1 Receive Activity Monitor. When set, this bit indicates that data is
currently being received by serial port 1. It is cleared when the internal hardware
sets the RI_1 bit. Do not alter the Clock Divide Control bits (PMR.7–6) while
this bit is set or serial port data may be lost.
Serial Port 0 Transmit Activity Monitor. When set, this bit indicates that data
is currently being transmitted by serial port 0. It is cleared when the internal
hardware sets the TI_1 bit. Do not alter the Clock Divide Control bits (PMR.7-6)
while this bit is set or serial port data may be lost.
Serial Port 0 Receive Activity Monitor. When set, this bit indicates that data is
currently being received by serial port 0. It is cleared when the internal hardware
sets the RI_1 bit. Do not alter the Clock Divide Control bits (PMR.7-6) while
this bit is set or serial port data may be lost.
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