DS80C320-MCG Datasheet, PDF (25/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

Clock Control (CKCON)
7
6
SFR 8Eh WD1 WD0
RW-0 RW-0
5
T2M
RW-0
4
T1M
RW-0
High-Speed Microcontroller User’s Guide
3
T0M
RW-0
2
MD2
RW-0
1
MD1
RW-0
0
MD0
RW-1
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
WD1, WD0
Bits 7-6
T2M
Bit 5
T1M
Bit 4
T0M
Bit 3
Watchdog Timer Mode Select 1-0. These bits determine the watchdog timer
time-out period. The timer divides the crystal frequency by a programmable
value as shown below. The divider value is expressed in clock (crystal) cycles.
The use of PMM1 or PMM2 will further divide the clock cycle count by either
16 or 256, respectively. Note that the reset time-out is 512 clocks longer than
the interrupt, regardless of whether the interrupt is enabled.
WD1
0
0
1
1
WD0
0
1
0
1
Interrupt Divider
2¹⁷
2²⁰
2²³
2²⁶
Reset Divider
2¹⁷ + 512
2²⁰ + 512
2²³ + 512
2²⁶ + 512
Timer 2 Clock Select. This bit controls the division of the system clock that
drives Timer 2. This bit has no effect when the timer is in baud rate generator or
clock output modes. Clearing this bit to 0 maintains 80C32 compatibility. This
bit has no effect on instruction cycle timing.
0 = Timer 2 uses a divide by 12 of the crystal frequency.
1 = Timer 2 uses a divide by 4 of the crystal frequency.
Timer 1 Clock Select. This bit controls the division of the system clock that
drives Timer 1. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 1 uses a divide by 12 of the crystal frequency.
1 = Timer 1 uses a divide by 4 of the crystal frequency.
Timer 0 Clock Select. This bit controls the division of the system clock that
drives Timer 0. Clearing this bit to 0 maintains 80C32 compatibility. This bit
has no effect on instruction cycle timing.
0 = Timer 0 uses a divide by 12 of the crystal frequency.
1 = Timer 0 uses a divide by 4 of the crystal frequency.
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