DS80C320-MCG Datasheet, PDF (108/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
Each interrupt source has an associated vector. This is the address to which the CPU will jump when the
interrupt occurs. When the interrupt condition occurs, the processor will also indicate this by setting a
flag bit. This bit is set regardless of whether the interrupt is enabled or not. That is, the flag responds to
the condition, not the interrupt. Most flags must be cleared manually by software. However, IE0 and IE1
are cleared automatically by hardware when the service routine is vectored to if the interrupt was edge
triggered. In level triggered mode, the flag follows the state of the pin. Flags TF0 and TF1 are always
cleared automatically when the service routine is vectored to. Refer to the individual bit descriptions
for more details. In order for the processor to acknowledge the interrupt and vector to the ISR, the
interrupt must be enabled. Each source has an independent enable as shown in Table 9-1.
Prior to using any source, interrupts must be globally enabled. This is done using the EA bit at location
IE.7. Setting this bit to a logic 1 allows individual interrupts to be enabled. Setting it to a logic 0 disables
all interrupts regardless of the individual interrupt enables. The only exception is the Power-fail
Interrupt. This is subject to its individual enable only. The EA bit has no effect on the Power-fail
Interrupt.
INTERRUPT SOURCES
Various combinations of interrupt sources are available on different members of the High-Speed
Microcontroller family. These are broken into several categories : External, Timer-based, Serial
Communication, real-time clock and Power Monitor. Each type is described below. Interrupt sources are
sampled once per machine cycle. If the source goes active after the sample, it will not be registered until
the next cycle.
External Interrupts
The High-Speed Microcontroller has 6 external interrupt sources. These include the standard 2 interrupts
of the 8051 architecture and 4 new sources. The original interrupts are INT0 and INT1. These are active
low, but can be programmed to be edge- or level-sensitive. The detection mode is controlled by bits IT0
and IT1, respectively. When ITx=0, the interrupt is triggered by a logic 0 on the appropriate interrupt
pin. The interrupt condition remains in force as long as the pin is low. When ITx=1, the interrupt is
pseudo edge-triggered. This means that if on successive samples, the pin is high then low, the interrupt is
activated.
Since the external interrupts are sampled, the pin driver of an edge-triggered interrupt should hold the
both the high, then the low condition for at least one machine cycles (each) to insure detection. This
means maximum sampling frequency on any interrupt pin is 1/8 of the main oscillator frequency.
It is important to note that level-sensitive interrupts are not latched. If the interrupt is level-sensitive, the
condition must be present until the processor can respond to the interrupt. This is most important if other
interrupts are being used with a higher or equal priority. If the device is currently processing another
interrupt, the condition must be present until the present interrupt is complete. This is because the level-
sensitive interrupt will not be sampled until the RETI instruction is executed.
The remaining 4 external interrupts are similar in nature, with two differences. First, INT2 and INT4 are
active high instead of active low. Second, all of the four new interrupts are edge-detect only. They do
not have level-detect modes. All associated bits and flags operate the same and have the same polarity as
the original two. A logic 1 indicates the presence of a condition, not the logic state of the pin.
108 of 175