DS80C320-MCG Datasheet, PDF (32/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

REN_0
Bit 4
TB8_0
Bit 3
RB8_0
Bit 2
TI_0
Bit 1
RI_0
Bit 0
High-Speed Microcontroller User’s Guide
Receiver Enable. This bit enable/disables the serial port 0 receiver shift
register.
0 = Serial port 0 reception disabled.
1= Serial port 0 receiver enabled (modes 1, 2, 3). Initiate synchronous reception
(mode 0).
9^th Transmission Bit State. This bit defines the state of the 9^th transmission bit
in serial port 0 modes 2 and 3.
9^th Received Bit State. This bit identifies that state of the 9^th reception bit of
received data in serial port 0 modes 2 and 3. In serial port mode 1, when
SM2_0=0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.
Transmitter Interrupt Flag. This bit indicates that data in the serial port 0
buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the
end of the 8^th data bit. In all other modes, this bit is set at the end of the last data
bit. This bit must be manually cleared by software.
Receiver Interrupt Flag. This bit indicates that a byte of data has been
received in the serial port 0 buffer. In serial port mode 0, RI_0 is set at the end of
the 8^th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming
stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last
sample of RB8_0. This bit must be manually cleared by software.
Serial Data Buffer 0 (SBUF0)
7
6
5
SFR 99h SBUF0.7 SBUF0.6 SBUF0.5
RW-0 RW-0 RW-0
4
SBUF0.4
RW-0
3
SBUF0.3
RW-0
2
SBUF0.2
RW-0
1
SBUF0.1
RW-0
0
SBUF0.0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
SBUF0.7-0
Bits 7-0
Serial Data Buffer 0. Data for serial port 0 is read from or written to this
location. The serial transmit and receive buffers are separate registers, but both
are addressed at this location.
Port 2 (P2)
7
SFR A0h P2.7
RW-1
6
P2.6
RW-1
5
P2.5
RW-1
4
P2.4
RW-1
3
P2.3
RW-1
2
P2.2
RW-1
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
1
P2.1
RW-1
0
P2.0
RW-1
P2.7-0
Bits 7-0
Port 2. This port functions as an address bus during external memory access,
and as a general purpose I/O port on devices which incorporate internal program
memory. During external memory cycles, this port will contain the MSB of the
address. The Port 2 latch does not control general purpose I/O pins on the
DS80C310 and DS80C320, but is still used to hold the address MSB during
register-indirect data memory operations such as MOVX A, @R1.
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