DS80C320-MCG Datasheet, PDF (92/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
POWER-FAIL RESET
Devices which incorporate the power-fail reset will automatically invoke a reset when V_CC drops below
V_RST. This will halt device operation, and place all outputs in their reset state. This state will continue to
be held until V_CC drops below the voltage necessary to power the port pins. Because V_RST is lower than
V_PFW, the microcontroller has the option to use the power-fail interrupt to place the device into a “safe”
state before the device halts operation with a power-fail reset. This feature is automatic on devices which
incorporate the power-fail reset feature, and cannot be disabled.
POWER ON RESET
When V_CC is applied to a system using the High-Speed Microcontroller, the device will hold itself in reset
until power is within tolerance and stable. An internal band-gap reference provides a highly accurate and
stable means of detecting power supply levels. It requires no external circuits to accomplish this. As
power rises, the processor will stay in a reset state until V_CC > V_RST. As V_CC rises above V_RST, internal
analog circuits will detect this and activate the on-chip crystal oscillator. On-chip hardware will then
count 65536 oscillator clocks. During this count, V_CC must remain above V_RST or the process restarts. If
an off-chip clock source is used, then clock counting still begins once V_CC > V_RST. This count period is
used to make certain that power is within tolerance, and that the oscillator has time to stabilize. This
provides a very controlled and predictable start-up condition.
Once the 65536 count period has elapsed, the reset condition is removed automatically, and software
execution will begin at the reset vector location of 0000h. Software will be able to detect the power on
reset condition using the Power-On Reset (POR) flag. POR is located at WDCON.6. This bit will be
high to indicate that a Power-on Reset has occurred. It should then be cleared by software.
The complete power cycle operation is shown in Figure 7-1. Note that the interrupt threshold is fixed, but
the interrupt itself is optional. Reset thresholds are also fixed and the reset operation is transparent. It
requires no external components and no action by software to control reset operation.
BAND-GAP SELECT
When present, the band-gap reference will provide a precise voltage reference for the power-fail monitor
circuitry. The band-gap is normally disabled automatically upon entering Stop mode to provide the
lowest power state. Since the band-gap is inactive, there can be no power-fail interrupt and no power-fail
reset, similar to a traditional 8051.
If the use of the power-fail features are desired in Stop mode, the BGS bit (EXIF, 91h) may be used.
When set to a logic 1 by software, the band-gap reference and associated power monitor circuits will
remain active in Stop mode. The price of this feature is higher power supply current requirements. In
Stop mode with the band-gap reference disabled (default), the processor draws approximately 1 µA.
With the band-gap enabled, it draws approximately 50 µA.
BGS allows the user to decide whether the control circuitry and its associated power consumption are
needed. If the application is such that power will not fail while in Stop or if it does not matter that power
fails, the BGS should be set to 0 (default). If power can fail at any time and cause problems, the BGS
should be set to 1.
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