DS80C320-MCG Datasheet, PDF (114/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
SECTION 10: PARALLEL I/O
The High-Speed Microcontroller method of implementing I/O ports follows the standard 8051
convention. This provides backward compatibility with existing designs. All drive capabilities exceed or
equal the original 80C32, and voltage levels are compatible. The transitions between strong and weak
drives are similar but not identical. Differences are to accommodate higher speed timing and the
associated demands on slew rates. As with any new technology, the High-Speed Microcontroller
should be evaluated in a system to see how subtle differences affect operation.
From a software perspective, each port appears as Special Function Register (SFR) with a unique address.
Each port register is addressable as a byte or 8 individual bit locations. The CPU distinguishes between a
bit access and a byte access by the instruction type. Except for the special cases mentioned below, the
register and port pins have identical states. Thus reading or writing a port is the same as reading or
writing the SFR for that port.
The microcontroller will distinguish between port and bus operations automatically. If a memory fetch is
decoded and requires external memory, Port 0 and 2 will be driven as a bus with the associated timing
and drive strengths. If either port SFR is accessed, the port pins will revert to the characteristics
described above. This includes a strong pull-down, a strong pull–up for transitions, and a weak pull-up
for static conditions.
ROMless versions of the High-Speed Microcontroller dedicate Port 0 and 2 as the memory interface bus.
The Port 0 latch does not exist on ROMless devices. The functions of these ports are described in more
detail in the specific sections.
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