DS80C320-MCG Datasheet, PDF (134/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
WATCHDOG TIMER
The Watchdog Timer is a user programmable clock counter that can serve as a time-base generator, an
event timer, or a system supervisor. As can be seen in the diagram of Figure 11-8, the timer is driven by
the main system clock that is supplied to a series of dividers. The divider output is selectable, and
determines the interval between time-outs. When the time-out is reached, an interrupt flag will be set,
and if enabled, a reset will occur. The interrupt flag will cause an interrupt to occur if its individual
enable bit is set and the global interrupt enable is set. The reset and interrupt are completely discrete
functions that may be acknowledged or ignored, together or separately for various applications.
WATCHDOG TIMER Figure 11-8
XTAL1
XTAL2
DIVIDE BY
1/16/256
RWT (WDCON.0
(Reset Watchdog)
DIVIDE BY DIVIDE BY DIVIDE BY DIVIDE BY
2¹⁷
2³
2³
2³
WD1 (CKCON.7)
WD0 (CKCON.6)
CLOCK DIVIDE CONTROL
CD1
CD0 DIVISOR
No PMR register 1
0
X
1
1
0
16
1
1
256
2¹⁷
2²⁰ 2²³
TIME-OUT
SELECTOR
2²⁶
TIME-OUT
WDIF
(WDCON.3)
EWDI (EIE.4)
(Enable Watchdog
512 CLOCK
DELAY
EWT (WDCON.1)
(Enable Watchdog Timer
WATCHDOG
INTERRUPT
RESET
WTRF
(WDCON.2)
The Watchdog Timer Reset function works as follows. After initializing the correct time-out interval
(discussed below), software first restarts the Watchdog using RWT(WDCON.0) and then enables the
reset mode by setting the Enable Watchdog Timer Reset (EWT = WDCON.1) bit. At any time prior to
reaching its user selected terminal value, software can set the Reset Watchdog Timer (RWT =
WDCON.0) bit. If RWT is set before the time-out is reached, the timer will start over. If the time-out is
reached without RWT being set, the Watchdog will reset the CPU. Hardware will automatically clear
RWT after software sets it. When the reset occurs, the Watchdog Timer Reset Flag (WTRF =
WDCON.2) will automatically be set to indicate the cause of the reset, however software must clear this
bit manually.
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