DS80C320-MCG Datasheet, PDF (115/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

High-Speed Microcontroller User’s Guide
PORT 0
General Purpose I/O
Devices which have internal program memory have the ability to use Port 0 as a general purpose I/O.
Data written to the port latch serves to set both level and direction of the data on the pin. ROMless
devices do not contain a Port 0 latch, because at no time can it be manipulated as a port. When used as an
I/O port, it functions as an open-drain output. More detail on the functions of these pins is provided
under the description of output and input functions in this section.
Even if internal memory is present, the use of Port 0 as general purpose I/O pins is not recommended if
the device will be used to access external memory. This is because the state of the pins will be disturbed
during the memory access. In addition, the pull-ups needed to maintain a high state during the use as
general purpose I/O will interfere with the complementary drivers employed when the device operates as
an expanded memory bus.
Multiplexed Address/Data Bus AD0-7
When used to address expanded memory, Port 0 functions as a multiplexed address/data bus. Port 0 must
function as the address/data bus on ROMless devices. Port 0 pins have extremely strong drivers that
allow the bus to move 100 pF loads with the timing shown in the electrical specifications. Special circuit
protection allows these pins to achieve the maximum slew rate without ringing, eliminating excessive
noise or interface problems. Users that compare the High-Speed Microcontroller family to 80C32
devices will find improved drive capability. This power is available for dynamic switching only, and
should not be used to drive heavy DC loads such as LEDs.
When used as an address bus, the AD0-7 pins will provide true drive capability for both logic levels. No
pull-ups are needed. In fact, pull-ups will degrade the memory interface timing. Members of the High-
Speed Microcontroller family employ a two-state drive system on AD0-7. That is, the pin is driven hard
for a period to allow the greatest possible setup or access time. Then the pin states are held in a weak
latch until forced to the next state or overwritten by an external device. This assures a smooth transition
between logic states and also allows a longer hold time. In general, the data is held (hold time) on AD0-7
until another device overwrites the bus. This latch effect is generally transparent to the user.
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