DS80C320-MCG Datasheet, PDF (51/175 Pages) Dallas Semiconductor – High-Speed Microcontroller User Guide

WDIF
Bit 3
EWT
X
0
0
1
1
WTRF
Bit 2
EWT
Bit 1
RWT
Bit 0
High-Speed Microcontroller User’s Guide
Watchdog Interrupt Flag. This bit, in conjunction with the Watchdog Timer
Interrupt Enable bit, EWDI (EIE.4), and Enable Watchdog Timer Reset bit
(WDCON.1), indicates if a watchdog timer event has occurred and what action
will be taken. This bit must be cleared in software before exiting the interrupt
service routine, or another interrupt will be generated. Setting this bit in
software will generate a watchdog interrupt if enabled. This bit can only be
modified using a Timed Access Procedure.
EWDI
X
0
1
0
1
WDIF
0
1
1
1
1
RESULT
No watchdog event has occurred.
Watchdog time-out has expired. No interrupt has been
generated.
Watchdog interrupt has occurred.
Watchdog time-out has expired. No interrupt has been
generated. Watchdog timer reset will occur in 512 cycles
if RWT is not strobed.
Watchdog interrupt has occurred. Watchdog timer reset
will occur in 512 cycles if RWT is not set using a Timed
Access procedure.
Watchdog Timer Reset Flag. When set, this bit indicates that a watchdog timer
reset has occurred. It is typically interrogated to determine if a reset was caused
by watchdog timer reset. It is cleared by a power- on reset, but otherwise must be
cleared by software before the next reset of any kind or software may
erroneously determine that a watchdog timer reset has occurred. Setting this bit
in software will not generate a watchdog timer reset. If the EWT bit is cleared,
the watchdog timer will have no effect on this bit.
Enable Watchdog Timer Reset. This bit enables/disables the ability of the
watchdog timer to reset the device. This bit has no effect on the ability of the
watchdog timer to generate a watchdog interrupt. The time-out period of the
watchdog timer is controlled by the Watchdog Timer Mode Select bits
(CKCON.7-6). Clearing this bit will disable the ability of the watchdog timer to
generate a reset, but have no affect on the timer itself, or its ability to generate a
watchdog timer interrupt. This bit can only be modified using a Timed Access
Procedure. The default power-on reset state of this bit is 0 on the ROMless
devices. If the device contains internal program memory, the default power-on
reset state of EWT is determined by the Watchdog Default POR State bit
(WDPOR) located in the System Control Byte or a mask option. This bit is
unaffected by all other resets.
0 = A timeout of the watchdog timer will not cause the device to reset.
1 = A timeout of the watchdog timer will cause the device to reset.
Reset Watchdog Timer. Setting this bit will reset the watchdog timer count.
This bit must be set using a Timed Access procedure before the watchdog timer
expires, or a watchdog timer reset and/or interrupt will be generated if enabled.
The time-out period is defined by the Watchdog Timer Mode Select bits
(CKCON.7-6). This bit will always be 0 when read.
51 of 175